Flat panel display apparatus and method of driving such panel

ABSTRACT

A flat panel display comprises a plurality of display elements (C) arranged in a matrix of rows (R) and columns, and first and second electrodes (Sc, Su) which are aligned with respect to each other and extend in a row or a column direction. The first and second electrodes (Sc, Su) form pairs which are associated with same display elements (C). An amount of electro-magnetical interference caused by currents through the first and second electrodes (Sc, Su) is decreased by driving the first and second electrodes (Sc, Su) in at least two groups such that the pairs are divided in two groups, and such that currents in pairs belonging to different groups flow in opposite directions.

The invention relates to a flat panel display apparatus, and a methodand apparatus for minimizing EMI radiations from the flat panel display.

Prior art U.S. Pat No. 5,541,618 discloses sub field driven flat paneldisplays. An embodiment describes a surface discharge type plasmadisplay panel (further referred to as PDP). A plurality of X-electrodeseach arranged parallel and close to a plurality of Y-electrodes, andaddress electrodes orthogonal to the X and Y electrodes are arranged ona surface of a panel. Electrodes crossing each other are insulated withan insulating layer. An address cell is formed at each crossing of theY-electrodes and the address electrodes. Display cells are formedbetween the Y-electrode and the adjacent X-electrode, close to thecorresponding address cells, respectively. An address period isperformed concurrently on all the Y-electrodes. In address periods, awrite pulse is applied to all the X-electrodes while a first sustainpulse that is opposite to the write pulse is applied to all theY-electrodes, and the address electrodes are kept at zero volts.Accordingly, all the display cells are discharged. Next, immediatelysubsequent to the write pulse a second sustain pulse opposite to thewrite pulse is applied to all the X-electrodes, so that a wall charge isgenerated in each display cell and a part of the associated addresscell. Next, an erase pulse is applied sequentially to each of theY-electrodes. Concurrently to the application of the erase pulse, anaddress pulse is selectively applied to an address electrode of adisplay cell not to be lit later during the subsequent display period byerasing a wall charge. At a cell to which no address pulse is applied,the wall charge is maintained and the cell will lit during thesubsequent display period.

In a first display period subsequent to the first address period,sustain pulses are applied to all the cells by applying first sustainpulses to all the Y-electrodes and second sustain pulses alternately toall X-electrodes. The cells with a wall charge are lit by the sustainpulses.

If the flat panel display is driven in a sub field mode, the abovementioned operations are repeated in the subsequent sub fields.

It is a drawback of the flat panel display apparatus of the prior artthat it generates a high amount of electro-magnetic interference(further referred to as EMI).

It is an object of the invention to provide a flat panel displayapparatus and a method for driving such an apparatus generating lessEMI.

To this end, the invention provides a method and apparatus for driving aflat panel display that drives two complementary sets of pairs ofelectrodes in the flat panel display with opposing currents.

A pair of scan and sustain electrodes (in the prior art referred to as Xand Y electrodes, in the claims referred to as first and secondelectrodes) is associated with each display cell (also referred to asdisplay element). A display cell may be a portion of a plasma channel atthe intersection of the a pair of scan and sustain electrodes and anaddress electrode (further referred to as data electrode). The plasmachannel may be aligned with the data electrodes or with the scan andsustain electrodes. The scan and sustain electrodes each are divided inat least two groups such that the pairs of scan and sustain electrodesare divided in at least two groups. Drive signals are supplied to thegroups of scan and sustain electrodes such that the currents in thepairs of scan and sustain electrodes belonging to different groups flowin opposite direction. The EMI generated due to the currents in acertain pair of scan and sustain electrodes is almost canceled by theEMI generated due to the currents flowing in the opposite direction in anearby situated pair of scan and sustain electrodes belonging to adifferent group. Consequently, the total amount of EMI decreases.

In the prior art all pairs of scan and sustain electrodes are driven ina same way. Consequently, all currents in the scan and sustainelectrodes have a same direction. This causes a high amount of EMI,especially during the display period (also referred to as sustainperiod) during which all scan and sustain electrodes are driven at thesame time.

In first embodiment of the invention, the drive circuit for driving thesustain electrodes is very simple as it consists of conductorsinterconnecting the sustain electrodes in groups.

In a another embodiment of the invention, pairs of scan and sustainelectrodes belonging to different groups alternate. In this way, amaximum compensation of the EMI generated by the two consecutive pairsis obtained, because a minimal area between successive pairs withopposite currents adds to the EMI, and a maximum correlation between thesignals on the rows exist.

These and other aspects of the invention will be apparent from andelucidated with reference to the accompanying drawings.

In the drawings:

FIG. 1 schematically illustrates a circuit for driving a PDP of asurface-discharge type in a sub field mode as known from the prior art,

FIG. 2 schematically illustrates a basic sub-pixel structure of asurface-discharge type PDP,

FIG. 3 shows voltage waveforms between a scan and a sustain electrode ofthe prior art surface-discharge type PDP,

FIGS. 4A, 4B, and 4C show voltages supplied to the scan and the sustainelectrodes during an erase period, a prime period and a sustain period,

FIG. 5 shows the voltages supplied to the groups of scan and sustainelectrodes according to an embodiment of the invention,

FIG. 6 shows a basic sub-circuit of the scan driver circuit, and

FIG. 7 shows the connections of sub-circuits during a sustain periodaccording to an embodiment of the invention.

FIG. 1 schematically illustrates a circuit for driving a PDP of asurface-discharge type in a sub field mode as known from the prior art.Two glass panels (not shown) are arranged opposite to each other. Dataelectrodes D are arranged on one of the glass panels. Pairs of scanelectrodes Sc and sustain electrodes Su are arranged on the other glasspanel. The scan electrodes Sc are aligned with the sustain electrodesSu, and the pairs of scan and sustain electrodes Sc, Su areperpendicular with respect to the data electrodes D. Display elements(for example plasma cells) C are formed at the cross points of the dataelectrodes D and the pairs of scan and sustain electrodes Sc, Su. Atiming generator 1 receives display information Pi to be displayed onthe PDP. The timing generator 1 divides a field period Tf of the displayinformation Pi into a predetermined number of consecutive sub fieldperiods Tsf (see FIG. 3). A sub field period Tsf comprises an addressperiod or prime period Tp and a display period or sustain period Ts.During an address period Tp, a scan driver 2 supplies pulses to the scanelectrodes Sc for successively selecting the scan electrodes Sc one byone, and a data driver 3 supplies data di to the data electrodes D towrite the data di to the display elements C associated with the selectedscan electrode Sc. In this way the display elements C associated withthe selected scan electrode Sc are preconditioned. A sustain driver 6drives the sustain electrodes Su. During an address period Tp, thesustain driver 6 supplies a fixed potential. During a display period Ts,a sustain pulse generator 5 generates sustain pulses Sp which aresupplied to the display elements C via the scan driver 2 and the sustaindriver 6. The display elements C, which are preconditioned during theaddress period Tp to produce light during the display period Ts, producean amount of light depending on a number or a frequency of the sustainpulses Sp. It is also possible to supply the sustain pulses Sp to eitherthe scan driver 2 or the sustain driver 6. It is also possible to supplythe sustain pulses Sp to the data driver 3 or both to the scan driver 2or the sustain driver 6 and the data driver 3.

The timing generator 1 further associates a fixed order of weightfactors Wf to the sub field periods Sf in every field period Tf. Thesustain pulse generator 5 is coupled to the timing generator 1 to supplya number or a frequency of the sustain pulses Sp in conformance with theweight factors Wf such that an amount of light generated by apreconditioned display element C corresponds to the weight factor Wf. Asub field data generator 4 performs an operation on the displayinformation Pi such that the data di is in conformance with the weightfactors Wf.

Such a PDP and the operation thereof in a sub field mode are describedin detail in U.S. Pat. No. 5,541,618 or in EP-B-0,549,275.

FIG. 2 schematically illustrates a basic AC plasma sub-pixel of asurface-discharge type PDP. The plasma sub-pixel or display element C isassociated to phosphor emitting one of the three primary colors. Theplasma sub-pixel C is formed by the crossing of two row electrodes Sc,Su and a column electrode Co. The two row electrodes Sc, Su are situatedat the bottom of the sub-pixel and are referred to as scan electrode Scand sustain electrode Su. The column electrode Co is situated on top ofthe sub pixel and is referred to as data electrode D. Plasma P isarranged between the column electrode Co and the two row electrodes Sc,Su via respective dielectric layers Di. The plasma P is insulated fromthe dielectric layers Di by MgO layers Mg. When regarding a completepanel, the sustain electrodes Su are interconnected for all rows of thePDP panel. The scan electrodes Sc are connected to row IC's and scannedduring the addressing or priming phase. The column electrodes Co areoperated by column IC's. The plasma cells C are operated in three modes:

1) The Erase mode. Before each sub-field is primed, all plasma cells Care erased together at the same time. This is done by first driving theplasma cells C into a conducting state and then removing all chargebuilt up in the cells C.

2) Prime mode. Plasma cells C are conditioned such that they will be inan on or off state during sustain mode. Since a plasma cell C can onlybe fully on or off, several prime phases are required to write all bitsof a luminance value. Plasma cells C are selected on a row-at-a-timebasis and the voltage levels on the columns Co will determine the on/offcondition of the cells. If a luminance value is represented in 6 bits,then also 6 sub-fields are defined within a field.

3) Sustain mode. An alternating voltage is applied to scan and sustainelectrodes Sc, Su of all rows together at the same time. The columnvoltage is mainly at a high voltage potential. The plasma cells C primedto be in the on state, will light up. The weight of an individualluminance bit will determine the number of light pulses during sustain.When the power dissipation of the panel is too high, the number ofsustain pulses in each sub-field is shortened to the same extent (soless sustain pulses are actually generated) thereby reducing the panel'slight output and power dissipation.

FIG. 3 shows voltage waveforms between scan electrodes Sc and sustainelectrodes Su of the known surface-discharge type PDP. Since there arethree modes, the corresponding time sequence is indicated as Te,bx(erase mode for bit-x subfield), Tp,bx (prime mode for bit-x subfieldSFi) and Ts,bx (sustain mode for bit-x subfield SFi. The number ofsustain pulses will vary in time to time limit the power dissipation soa residual time Tr is taken into account to match the field frequencyagain.

FIG. 4 shows result of a measurement of the differential voltage betweena scan and the common sustain electrodes Sc, Su when this voltage ismeasured over a field.

FIG. 4 only gives a rough indication of what happens in a field periodTf.

Prime and erase sequences in each subfield SFi are the same. Theduration of the sustain sequence depends on the weight of the individualbits and contains a number of alternating pulses with the samefrequency. When the power dissipation of the panel is too high, thenumber of alternating pulses during sustain time Ts,bx will be less.This results in shorter sustain periods Ts,bx in the sub-fields SFi andthe residual time T_(r) will increase to match the field frequency.

TABLE 1 Timing in erase, prime and sustain modes. bit- bit- 5[μs] 4[μs]bit-3[μs] bit-2[μs] bit-1[μs] bit-0[μs] Tp. 6 × 1800 black Ts. 1737 854432[43c] 221[21c] 115[l0c] 57[4c] black [179c] [87c] Te. 6 × 168  blackTr. 1 × 1443 black Tp. 6 × 1800 white Ts. 1017 499 259[25c] 125[llc] 67[5c] 38[2c] white [104c] [50c] Te. 6 × 168  white Tr. 1 × 2854 white

Table 1 gives an overview of the panel's timing when an over-all black(level 0) or white (level 63) picture is displayed. As can be seen fromthe table, the prime and erase modes are not changed when the powerdissipation is limited by the electronics. The number of sustain pulsesis roughly halved when a complete white picture is displayed. The numberof sustain pulses is also given in the table (pulse count can be foundbetween brackets in the Ts-rows). Equation 1 can be used to calculatedthe sustain time Ts,bx in a subfield SFi.

Ts,bx=T _(sustain)=19+9.6.N [μs]  (Equation 1)

The variable N stands for pulse count, printed in the table. Each pulsetakes 9.6 μs and N pulses are always preceded by a specified sequence of19 μs.

FIGS. 4A, 4B, and 4C show voltages supplied to the scan and the sustainelectrodes Sc, Su during an erase period Te, a prime period Tp and asustain period Ts, respectively. In the AC plasma display panel shown inFIGS. 4A, 4B, and 4C, each plasma cell C (further referred to as cell)is addressed with two row electrodes (the scan and the sustainelectrodes Sci, Sui) and one column electrode (the data electrode Dj). AVGA display may consists of 480*(3*852) cells C. The number of rows Riis 480, the number of pixels in a row is 852, and a pixel consists ofthree adjacent cells CR, CG, CB, one for each of the three primarycolors.

FIG. 4A shows voltages applied to the electrodes Sc, Su, D during theerase period Te. A sequence of scan voltages Vsc applied to the scanelectrodes Sc is denoted by five numbers arranged in a column at theleft side of the plasma panel. The five numbers correspond to fiveconsecutive sub periods of the erase period Te. The first number of thecolumn denotes the value of the scan voltage Vsc during a first subperiod of the erase period Te, the fifth number in the column denotesthe value of the scan voltage Vsc during the last sub period of theerase period Te. All scan electrodes Sc are interconnected. A sequenceof sustain voltages Vsu applied to the sustain electrodes Su is denotedat the right side of the plasma panel. All sustain electrodes Su areinterconnected. A sequence of data voltages Vd applied to the dataelectrodes D is denoted at the right side of the plasma panel. Voltagevalues which have a same vertical position in a column belong to a samesub period of the erase period Te. For example, during the third subperiod of the erase period Te, the scan voltage Vsc is minus 160 volts,the sustain voltage Vsu is zero volts, and the data voltage is zerovolts. After the erase period Te, all cells are erased.

FIG. 4B shows the scan voltage Vsc, the sustain voltage Vsu, and thedata voltage Vd during a sub period of the prime period Tp. The scanvoltage Vsc of the selected row Rs has a value of minus 170 volts. Toall other rows Ri, a scan voltage Vsc of minus 70 volts is applied. Allsustain electrodes Su are interconnected and receive a sustain voltageof 50 volts. The data voltage Vd has either a value of zero volts or 60volts to precondition a cell C to stay dark or to emit light,respectively, during the subsequent sustain period Ts. During the primeperiod Tp all rows are selected subsequently to precondition all thecells C row by row. Only the primed cells C will ignite during thesustain period.

FIG. 4C shows the scan voltage Vsc, the sustain voltage Vsu, and thedata voltage Vd during the sustain period Ts, as applied in the priorart. The scan voltage Vsc is applied to the scan electrodes Sc which areall interconnected. The sustain voltage Vsu is applied to the sustainelectrodes Su which are all interconnected. The data electrodes D supplya data voltage Vd with a value of 60 volts. The sustain period Tscomprise sustain pulses Sp with a typical repetition time of about 20us. A sustain pulse Sp comprises two consecutive periods, a first periodduring which the scan voltage Vsc is 170 volts and the sustain voltageVsu is zero volts, and a second period during which the scan voltage Vscis zero volts and the sustain voltage Vsu is 170 volts. During thesustain period Ts, large currents flow in the rows R of the PDP tocreate the light output. A maximum current of about 300 mA flows in eachrow R of a 42″ PDP when a white line has to be displayed. Consequently,a total display peak current of 144 ampere with a frequency of about 50kHz flows in a VGA display with 480 rows R if a white plane has to bedisplayed. This introduces a lot of EMI. Let us assume that the totalreturn current is collected at the back of the PDP in the middle. So,the total current is supplied to, or withdrawn from the scan electrodesSc via a scan conductor connected to the scan electrode Sc arranged inthe middle of the PDP, and the total current is supplied to or withdrawnfrom the sustain electrodes Su via a sustain conductor connected to thesustain electrode Su arranged in the middle of the PDP. Both the scanand the sustain conductor end at the right side of the PDP near to eachother. The area enclosed by the current loops is different for each rowR. Let us assume that the area enclosed by one row R is indicated byAr=Ap/480, wherein Ap is the area of the PDP and 480 is the numbers ofrows of the PDP. The total area enclosed by the currents equalsapproximately:

Atotal=2*(1+2+ . . . +240)*Ar=57840 Ar.

This total area Atotal is a measure for the amount of EMI generated bythe PDP.

FIG. 5 shows the voltages supplied to the groups of scan and sustainelectrodes Sc, Su during the sustain period Ts according to anembodiment of the invention. The scan electrodes Sc and the sustainelectrodes Su both are divided in two groups. All scan electrodes Sco ofodd rows Ro are interconnected to receive a first voltage V1, and allscan electrodes Sce of even rows are interconnected to receive a secondvoltage V2. All sustain electrodes Suo of the odd rows areinterconnected to receive the second voltage V2, and all sustainelectrodes Sue of the even rows are interconnected to receive the firstvoltage V1. Both the first voltage V1 and the second voltage V2 havealternately a value of zero and 170 volts. The first voltage V1 is zerovolts if the second voltage V2 has a value of 170 volts, and the otherway around. In this way, the currents flowing in the scan and sustainelectrodes Sc, Su of successive rows R have opposite directions. Theelectromagnetic field generated by the current through a particular oddrow Ro is almost compensated by the electro-magnetic field generated bya successive even row Re. Only the area between the odd and even row Ro,Re adds to the EMI. So, the area enclosed by the currents in a VGA PDPwith 480 rows R is approximately 480*Ar. Consequently, with respect tothe prior art a reduction in EMI is obtained of about20*log(57840/480)=42 dB. This calculation of the EMI reduction is basedon a first order approximation, in a practical three-dimensional set-upa reduction of 20 to 25 dB has been measured.

An optimal reduction of the EMI is reached by generating oppositecurrents in successive rows R. In this way, a maximum compensation ofthe EMI generated by the two consecutive pairs is obtained, because aminimal area between successive pairs with opposite currents adds to theEMI, and a maximum correlation between the display signals on the rowsexist.

It is also possible to reduce the EMI if the PDP is divided in blocks ofn (for example 16) successive rows R in which the current flows in asame direction followed by a block of successive rows R in which thecurrent flows in a direction opposite to the current direction of thepreceding block of successive rows R.

FIG. 6 shows a basic sub-circuit 20 of the scan driver circuit 2. Thebasic sub-circuit 20 of FIG. 6 comprises a first field effect transistor(FET) 22 with a main current path arranged in series with a main currentpath of a second FET 24. First and second diodes 23, 25 are theparasitic diodes of the first and second FET, respectively. A controlcircuit 21 receives an input control signal on input I and suppliescontrol signals to control electrodes of the first and the second FET22, 24. The interconnected main terminals of the first and the secondFET 22, 24 are connected to a terminal C. Terminal C is connected to oneof the scan electrodes Sc. The yet free main terminal of the first FET22 is connected to a terminal B, and the yet free main terminal of thesecond FET 24 is connected to a terminal A.

During the prime period Tp, a first negative voltage (for example: −70V) is applied to the terminal B, and a second negative voltage (forexample: −170 V) is applied to the terminal A. The input control signalapplied to the input terminal I determines whether the first FET 22 orthe second FET 24 is conductive. If the first FET 22 is conductive, thefirst negative voltage is supplied to the scan electrode Sc and theassociated row is not selected. If the second FET 24 is conductive, thesecond negative voltage is supplied to the scan electrode Sc and theassociated row is selected.

A sub-circuit 20 is connected to every scan electrode Sc to enablepriming of the rows R one by one (the cells C associated with theselected row R are preconditioned) by applying appropriate input controlsignals to respective inputs I of the control circuits 21.

In contrast to the prime period Tp during which the rows R need to beselected one by one, during the sustain period Ts it is advantageous tosustain all rows R at the same time. As no selection per row R isneeded, in every sub-circuit 20, the control circuits 21 control thefirst and the second FET 22, 24 to be non-conductive. So, only the firstand second diodes 23, 25 are relevant during the sustain period Ts.During a first period of a sustain pulse Sp, a high positive voltage(for example: +170 V) is applied to terminal A, while terminal B is openended. A current I1 flows from terminal A via diode 25 to the scanelectrode Sc connected to terminal C. During a second period of asustain pulse Sp, a low voltage (for example: 0 V) is applied toterminal B, while terminal A is open ended. A current I2 flows fromterminal C via diode 23 to terminal B.

FIG. 7 shows the connections of sub-circuits 20 i during a sustainperiod Ts according to an embodiment of the invention. As discussedearlier, only the first and second diodes 23, 25 are relevant during thesustain period Ts. Therefore, FIG. 7 only shows the first and seconddiodes 23, 25 of each sub-circuit 20. A sub drive circuit 2 e comprisesthe left column of sub-circuits 20 e with first and second diodes 23 e,25 e to drive the scan electrodes Sce of the even rows Re. A sub drivecircuit 20 comprises the right column of sub-circuits 20 o with firstand second diodes 23 o, 25 o to drive the scan electrodes Sco of the oddrows Ro. All terminals Ao of the sub-circuits 20 o in the right columnare connected to a first contact 1 of a first switch S1. All terminalsBo of the sub-circuits 20 o are connected to a second contact 2 of thefirst switch S1. All terminals Be of the sub-circuits 20 e in the leftcolumn are connected to a first contact 1 of a second switch S2. Allterminals Ae of the sub-circuits 20 e are connected to a second contact2 of the second switch S2. A common contact of the first switch S1receives a first voltage V1 from the sustain pulse driver 5. and acommon contact of the second switch S2 receives a second voltage V2 fromthe sustain pulse driver 5. The first voltage V1 is also applied to theeven sustain electrodes Sue, via a sub drive circuit 6 e. The secondvoltage V2 is also applied to the odd sustain electrodes Suo, via a subdrive circuit 6 o. As shown, in a preferred embodiment, the sub drivecircuits 6 e and 6 o are conductors. Both the first and the secondswitch S1, S2 connect their common contact with contact 1 if the firstvoltage V1 has a high level (for example: 170 V), and both the first andthe second switch S1, S2 connect their common contact with contact 2 ifthe first voltage V1 has a low value (for example: 0 V). In this way,during the period in time the first voltage V1 has a high voltage andthe second voltage V2 has a low value, currents in the odd scan andsustain electrodes Sco, Suo flow from left to right and currents in theeven scan and sustain electrodes Sce, Sue flow from right to left, asindicated by the arrows. During the time the first voltage V1 has a lowvalue and the second voltage V2 has a high value, all the currentschange direction. Again, the currents in odd and even electrodes Sco,Sce, Suo, Sue flow in opposite directions. The data electrodes D aredriven by the data driver 3.

The first and the second switch may be omitted if impedance's of theconductors between the first and the second switch contacts 1, 2 arenegligible. In this case the first and the second contact 1, 2 of thefirst switch S1 may be interconnected to receive the first voltage V1,and the first and the second contact 1, 2 of the second switch S2 may beinterconnected to receive the second voltage V2.

While the invention has been described in connection with preferredembodiments, it will be understood that modifications thereof within theprinciples outlined above will be evident to those skilled in the artand thus the invention is not limited to the preferred embodiments butis intended to en compass such modifications. All values of voltages areexamples. The invention is not restricted to a PDP with a certainresolution or a certain number of rows R. It is possible to interchangethe row and column directions, the scan and sustain electrodes Sc, Sumay extend in the column direction. The invention is also suitable forflat panel displays which are driven in an other mode than a sub fieldmode. The invention is also not restricted to a PDP in which a differentpair of electrodes (one scan and one sustain electrode) Sc, Su areassociated to each row R of cells C. With some minor changes it is alsopossible to generate currents with opposite directions in a PDP in whichtwo rows R of cells C are driven with three electrodes instead of fourelectrodes. In such a PDP a first row R of cells C is associated to afirst scan electrode Sc and a sustain electrode Su, and a second row Rof cells is associated to the same sustain electrode Su and a secondscan electrode Sc, and so on. The sustain electrodes Su are divided intwo groups such that two sustain electrodes Su arranged on either sideof a scan electrode Sc belong to different groups. In this way, thepriming of only one row R of cells C is possible by applying appropriatevoltages to the scan electrode Sc and the adjacent sustain electrodesSu. By further dividing the groups of sustain electrodes Su it ispossible to obtain groups of pairs of sustain electrodes Su and scanelectrodes Sc, whereby the currents in pairs belonging to differentgroups flow in opposite directions.

What is claimed is:
 1. A flat panel display apparatus comprising: a flatpanel display having a plurality of display elements (C) arranged in amatrix of rows (R) and columns, and first and second electrodes (Sc, Su)being aligned with respect to each other and extending in a row or acolumn direction, the first and second electrodes (Sc, Su) forming pairsbeing associated with same display elements (C), and a drive circuit (2,6) being coupled to the first and second electrodes (Sc, Su) forsupplying drive signals to said pairs, characterized in that the drivecircuit (2, 6) comprises sub drive circuits (2 o, 2 e, 6 o, 6 e) forsupplying opposite drive signals (V1, V2) to different groups of pairssuch that currents flowing in pairs of two different groups flow inopposite direction.
 2. A flat panel display apparatus as claimed inclaim 1, characterized in that a first one of the sub drive circuits (2o) is coupled to a first group of first electrodes (Sco), a second oneof the sub drive circuits (2 e) is coupled to a second group of firstelectrodes (Sce), a third one of the sub drive circuits (6 o) is coupledto a first group of second electrodes (Suo), a fourth one of the subdrive circuits (6 e) is coupled to a second group of second electrodes(Sue), the first group of second electrodes (Suo) being associated withsame display elements (C) as corresponding first electrodes (Sco) of thefirst group of first electrodes, the second group (Sue) ofinterconnected second electrodes being associated with same displayelements (C) as corresponding first electrodes (Sce) of the second groupof first electrodes, the first and the fourth sub drive circuit (2 o, 6e) supplying substantially equal first drive signals (V1), the secondand third sub drive circuit (2 e, 6 o) supplying substantially equalsecond drive signals (V2), the first drive signal (V1) and the seconddrive signal (V2) occurring substantially in antiphase.
 3. A flat paneldisplay apparatus as claimed in claim 2, characterized in that the thirdsub drive circuit (6 o) comprises a conductor interconnecting the firstgroup of second electrodes (Suo), in that the fourth sub drive circuit(6 e) comprises a conductor interconnecting the second group of secondelectrodes (Sue).
 4. A flat panel display apparatus as claimed in claim1, characterized in that said pairs of two different groups alternate.5. A method of driving a flat panel display apparatus, the flat paneldisplay apparatus comprising a flat panel display having a plurality ofdisplay elements (C) arranged in a matrix of rows (R) and columns, andfirst and second electrodes (Sc, Su) being aligned with respect to eachother and extending in a row or a column direction, the first and secondelectrodes (Sc, Su) forming pairs being associated with same displayelements (C), and the method comprising the step of driving (2, 6) thefirst and second electrodes (Sc, Su) by supplying drive signals to saidpairs, characterized in that the step of driving (2, 6) comprises thesteps of supplying (2 o, 2 e, 6 o, 6 e) opposite drive signals todifferent groups of pairs such that currents flowing in pairs of twodifferent groups flow in opposite direction.